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Publication Type : Conference Paper
Publisher : IEEE
Source : 2025 8th International Conference on Trends in Electronics and Informatics (ICOEI)
Url : https://doi.org/10.1109/icoei65986.2025.11013533
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2025
Abstract : Dynamic Random Access Memory (DRAM) scaling is becoming increasingly questionable in terms of reliability and at the same time efficient Error Control Coding (ECC) architectures are needed to solve data correctness problems without impacting system performance too severely. This paper proposes an optimized reliable Content Addressable Memory (CAM) architecture for DRAMs. The proposed architecture employs a slightly larger base circuit, resulting in a 2 % increase in area while reducing power consumption by 3.63%. Although in contrast with current systems, the proposed solution improves the reliability of DRAM and CAM without any loss of existing features.
Cite this Research Publication : R. S. R. Likhith, R. Sooraj, V. Sasikamal and M. Vinodhini, "Optimized Reliable Content Addressable Memory," 2025 8th International Conference on Trends in Electronics and Informatics (ICOEI), Tirunelveli, India, 2025, pp. 399-403, doi: 10.1109/ICOEI65986.2025.11013533.