Publication Type:

Conference Paper

Source:

2011 IEEE Recent Advances in Intelligent Computational Systems, RAICS 2011, Trivandrum, Kerala, p.352-356 (2011)

ISBN:

9781424494774

URL:

http://www.scopus.com/inward/record.url?eid=2-s2.0-81355132822&partnerID=40&md5=662dabbf3837d1af60794c1903371cb2

Keywords:

Architecture, Arithmetic operations, Computational complexity, DSP application, Electron multipliers, Modelsim, Modified booth multipliers, Multiplier architecture, Power analysis, Power efficient, Power-aware, Quartus II, Re-configurable, Recursive architecture, Run time reconfiguration, Runtimes, Timing Analysis, Verilog

Abstract:

<p>Multiplier is one of the major arithmetic operations carried out in DSP applications. Multiplier architecture is reconfigured so as to enhance their performance and thereby improving the efficiency of the applications. This Reconfigurable multiplier is adapted at run time to satisfy multiple precision requirements of DSP applications. Power consumption of the multipliers is reduced with the introduction of power efficient scheme Dynamic Operand Interchange to the reconfigurable booth architecture. Implementation is done in Verilog and simulated using MODELSIM. Power and Timing analysis is done using Altera Quartus II tool (version 9.0) © 2011 IEEE.</p>

Notes:

cited By (since 1996)0; Conference of org.apache.xalan.xsltc.dom.DOMAdapter@47916ac5 ; Conference Date: org.apache.xalan.xsltc.dom.DOMAdapter@1bf8d038 Through org.apache.xalan.xsltc.dom.DOMAdapter@6c2e1ae0; Conference Code:87395

Cite this Research Publication

S. S. Sakthi and Kayalvizhi, N. M. N., “Power aware and high speed reconfigurable modified booth multiplier”, in 2011 IEEE Recent Advances in Intelligent Computational Systems, RAICS 2011, Trivandrum, Kerala, 2011, pp. 352-356.