Publication

Abstract : This paper presents three different circuits for D-latch designed using bulk-driven MCML topology for high-frequency and low-power applications. The BD-MCML topology is the combination of the bulk-driven technology with MCML technology. The number of MOSFETs used in BD-MCML topology is less compared to MCML topology as the BD-MCML topology uses bulk terminal as one of the input. The three proposed circuits are designed using 45 nm technology and analyzed using Cadence Virtuoso with a supply voltage of 0.6 V. The performance of all the proposed D-latch circuits is evaluated and compared with the existing bulk-driven MCML D-latch circuit concerning metrics like power, delay, rise time, and fall time. This paper concludes that the proposed BD-MCML D-latch circuits are power efficient when compared with the existing BD-MCML D-latch.