Publication Type:

Conference Paper

Source:

23rd International Conference on Field Programmable Logic and Applications (FPL), 2013 , IEEE, Porto (2013)

URL:

http://www.scopus.com/record/display.url?eid=2-s2.0-84898618444&origin=resultslist&sort=plf-f&src=s&st1=Shadow+And-Inverter+Cones&sid=9F816727778C5E0467E6037EBF626F71.N5T5nM1aaTEF8rE6yKCR3A%3a20&sot=b&sdt=b&sl=30&s=ALL%28Shadow+And-Inverter+Cones%29&relpo

Keywords:

Benchmark testing, Clustering algorithms, Delays, Field programmable gate arrays, Inverters, routing, Table lookup

Abstract:

Despite their many advantages, FPGAs still come with significant overheads in area, delay, and power consumption due to an extreme programmability in both the routing and logic. From the performance perspective, large logic blocks, capable of covering big portions of circuits, lead to fewer hops in the routing network, and thus, to a shorter critical path. Recent work has shown that And-Inverter Cones (AICs) can considerably reduce the number of logic block levels compared to Look-Up Tables (LUTs), in a radically altered FPGAs architecture. In this paper, we use AICs as shadow logic for LUTs, which incurs minimal architectural changes with respect to current FPGAs, while exploiting the benefits of both AICs and LUTs. We also propose changes in the AIC architecture, for a more compact technology mapping. The new architecture reduces the average circuit delay by up to 35% with respect to standard FPGAs at the expense of a 3x increase in the number of the logic clusters. Other benchmarks show more moderate area overheads, e.g., 16% delay improvement for 20% area overhead.

Cite this Research Publication

H. Parandeh-Afshar, Zgheib, G., Novo, D., Purnaprajna, M., and Ienne, P., “Shadow And-Inverter Cones”, in 23rd International Conference on Field Programmable Logic and Applications (FPL), 2013 , Porto, 2013.