Publication Type:

Journal Article

Source:

INTERNATIONAL ARAB JOURNAL OF INFORMATION TECHNOLOGY, ZARKA PRIVATE UNIV COLL COMPUTING & INFORMATION SOC, PO BOX 132222, ZARQA …, Volume 15, Number 3, p.469–478 (2018)

URL:

http://iajit.org/PDF/May%202018,%20No.%203/9077.pdf

Keywords:

Arbiter, chip area., latency, network calculus, Network topology, vertical links

Abstract:

Design of a topology and its router plays a vital role in a 3D Network-on-Chip (3D NoC) architecture. In this paper, we develop a partially vertically connected topology, so called 3D Recursive Network Topology (3D RNT) and using an analytical model, we study the performance of the 3D RNT. Delay per Buffer Size (DBS) and Chip Area per Buffer Size (CABS) are the parameters considered for the performance evaluation. Our experimental results show that the vertical links are cut down upto 75% in 3D RNT compared to that of 3D Fully connected Mesh Topology (3D FMT) at the cost of increasing DBS by 8%, besides 10% lesser CABS is observed in the 3D RNT. Further, a Programmable Prefix router-Arbiter (PPA) is designed for 3D NoC and its performance is analyzed. The results of the experimental analysis indicate that PPA has lesser delay and area (gate count) compared to Round Robin Arbiter (RRA) with prefix network

Cite this Research Publication

Nallasamy Viswanathan, Kuppusamy Paramasivam, and Dr. Somasundaram K., “Vertical Links Minimized 3D NoC Topology and Router-Arbiter Design”, INTERNATIONAL ARAB JOURNAL OF INFORMATION TECHNOLOGY, vol. 15, pp. 469–478, 2018.