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Interface Engineering for 3-Bit per Cell Multilevel Resistive Switching in AlN Based Memristor

Publication Type : Journal Article

Publisher : Institute of Electrical and Electronics Engineers (IEEE)

Source : IEEE Electron Device Letters

Url : https://doi.org/10.1109/led.2021.3125151

Campus : Chennai

School : School of Engineering

Year : 2021

Abstract : Gradual conduction tuning with a large memory window is essential for realizing multilevel switching memristive devices. In this work, we demonstrated 3-bit per cell storage capability with excellent endurance and retention behavior of AlN/AlO memristor via interface engineering. By incorporating an ultra-thin 2 nm Al2O3 interface layer, seven distinct high resistance states with same low resistance state were achieved by controlling reset-stop voltage. In addition, by varying set compliance current, six resistance states with reliability and reproducibility were illustrated. The maximum cycle-to-cycle variability σ/μ (standard deviation/mean) of any resistance state was 28.7% in reset-stop voltage control methods. The multilevel switching characteristics could be attributed to (a) enhancement of on-off ratio resulted due to insertion of Al2O3 barrier layer acts as series resistance (b) the gradual electron detrapping from occupied trap sites resulting in multiple intermediate resistance states during reset.

Cite this Research Publication : Srikant Kumar Mohanty, Poshan Kumar Reddy, Om Kumar Prasad, Chien-Hung Wu, Kow-Ming Chang, Jia-Chuan Lin, Interface Engineering for 3-Bit per Cell Multilevel Resistive Switching in AlN Based Memristor, IEEE Electron Device Letters, Institute of Electrical and Electronics Engineers (IEEE), 2021, https://doi.org/10.1109/led.2021.3125151

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