Publication Type : Conference Proceedings
Publisher : IEEE
Url : https://doi.org/10.1109/SCEECS61402.2024.10482181
Keywords : Performance evaluation; Computer science; MOSFET; Logic gates; Ions; Delays; Electrostatics; Graded Doped (GD); Junctionless Gate All Around (JGAA); Short Channel Effects (SCEs); Dual Gate (DG); Field Effect Transistor (FET)
Campus : Faridabad
School : School of Artificial Intelligence
Year : 2024
Abstract : In this article analysis the Graded doped Junctionless Gate All Around (GD-JGAA) MOSFETs and find that the electrostatic performance of the proposed devices GD-JGAA and compared to the JGAA MOSFET. As a result, find that the SS and DIBL are minimum in GD-JGAA MOSFET. So that the SCEs are reduced in GD-JGAA MOSFET as compared to JGAA MOSFET. Also find that the subthreshold current (IOFF) is minimal as well as the ION current also reduced. As a result, the ION/IOFF current ratio improved. So that the power delay performance increased in GD-JGAA MOSFET. So, that the device GD-JGAA MOSFET is most suitable for digital applications.
Cite this Research Publication : Alok Kumar, Bhavana P. Shrivastava, Tarun Kumar Gupta, Vivek Patel, Vidyadhar Gupta, Electrostatic Performance Enhanced in a Graded Doped Junctionless Gate All Around MOSFET, [source], IEEE, 2024, https://doi.org/10.1109/SCEECS61402.2024.10482181