Publication Type : Conference Paper
Publisher : Springer Nature Singapore
Source : Lecture Notes in Electrical Engineering
Url : https://doi.org/10.1007/978-981-97-6465-5_1
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2024
Abstract : Network on Chip (NoC) performance degradation is significantly impacted by network congestion. Routers using adaptive algorithms, which are capable of detecting traffic congestion, can enable NoC to support complex and dynamic applications. Additionally, there is a growing need in NoC for routing algorithms that can be modified to provide minimal paths and congestion monitoring. The proposed high-speed odd-even congestion-aware routing algorithm for NoC architecture is based on the odd-even turn model and regional congestion awareness. In terms of delay and throughput, the suggested technique performs better than the current algorithm.
Cite this Research Publication : Bellala Navyasri, Sankurathri Shreyaswi, Veerendra Sai Manasali, M. Vinodhini, High-Speed Congestion Aware Routing Algorithm for Network on Chip Architecture, Lecture Notes in Electrical Engineering, Springer Nature Singapore, 2024, https://doi.org/10.1007/978-981-97-6465-5_1