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Verilog Based Efficient Traffic Light System

Publication Type : Journal Article

Publisher : IEEE

Source : 2024 4th Asian Conference on Innovation in Technology (ASIANCON)

Url : https://doi.org/10.1109/asiancon62057.2024.10838078

Campus : Amritapuri

School : School of Engineering

Center : Humanitarian Technology (HuT) Labs

Department : Electronics and Communication

Year : 2024

Abstract : Traffic management is crucial for reducing congestion, minimizing delays, and ensuring safety at intersections. This paper presents the design and verification of an efficient Traffic Light System using Verilog Language. The system controls traffic at a four-way intersection, considering vehicle counts, pedestrian requests, and emergency signals. The design is implemented using a Finite State Machine (FSM) approach, with a comprehensive testbench developed to validate its functionality under various scenarios. The results demonstrate the system's ability to manage traffic efficiently, respond to pedestrian crossings, and handle emergency situations, thereby improving overall traffic flow and safety. The system's adaptability and responsiveness highlight its potential for real-world applications, addressing the limitations of traditional traffic light systems. Also, Verilog HDL ensures that the system is robust, scalable, and capable of being integrated into larger traffic management frameworks.

Cite this Research Publication : Poorna Shashank Gunna, Leela Sai Srinivas Ontipuli, Rajesh Kannan Megalingam, Verilog Based Efficient Traffic Light System, 2024 4th Asian Conference on Innovation in Technology (ASIANCON), IEEE, 2024, https://doi.org/10.1109/asiancon62057.2024.10838078

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