Course

Unit I

Introduction to Electronic System Level Design– Hybrid Design – ESLD Flows and Methodologies – Architecture Exploration–Hardware-software Partitioning.

Unit II

Models for ESL Design– Open-Source Languages–SpecC–ArchC and SystemC for ESLD– Transaction Level Modelling Building Platform Models in SystemC.

Unit III

High Level Synthesis– ESL Verification – Virtual Platform and Virtual Prototyping– Debugging SystemC Platform Models –SystemC Based Power Evaluation –SystemC Standards and Accellera Initiatives ESLD – Project Based Practice design

Learning Objectives

LO1 To introduce design and verification at system level.

LO2 To introduce open-source language-based design and debug.

LO3 To provide basics of Transaction Level Modelling and High-Level Synthesis.

LO4 To introduce portable test and stimulus standards.

Course Outcomes

CO1 Ability to understand Electronic System level Design and Verification.
CO2 Ability to apply system level design methodologies using open-source languages.

CO3 Ability to analyse virtual prototyping and its advantages.

CO4 Ability to evaluate the transaction level models built using SystemC.

CO-PO Mapping

References

1. Sandro Rigo, Rodolfo Azevedo and Luizsantos, Electronic System Level Design – An Open-Source Approach, Springer,