- Introduction to HDL simulation flow
- Structural and Dataflow Modeling in Verilog
- Behavioral Modeling and Verfication of combinational subsystems
- Behavioral Modeling, Synthesis and FPGA implementation of combinational subsystems
- Behavioral Modeling and Verfication of flip-flops, registers and counters
- Behavioral Modeling and Verification of Finite State Machines
- Behavioral Modeling, Synthesis and FPGA implementation of flip-flops, registers and counters
- Behavioral Modeling, Synthesis and FPGA implementation of Finite State Machines
- Case Study – RTL Architecture, Modeling and Verification of a Complete Digital System
- Case Study – RTL Architecture Modeling, Synthesis and FPGA Implementation of a Complete Digital System
NB: Scripting exercises with standard tools to be included wherever appropriate.
Recommended Tools: ModelSim, Vivado