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Course Detail

Course Name RTL Design and FPGA Synthesis Laboratory
Course Code 25VL682
Program M. Tech. in VLSI Design
Credits 1
Campus Amritapuri, Coimbatore, Bengaluru, Chennai

Syllabus

  1. Introduction to HDL simulation flow
  2. Structural and Dataflow Modeling in Verilog
  3. Behavioral Modeling and Verfication of combinational subsystems
  4. Behavioral Modeling, Synthesis and FPGA implementation of combinational subsystems
  5. Behavioral Modeling and Verfication of flip-flops, registers and counters
  6. Behavioral Modeling and Verification of Finite State Machines
  7. Behavioral Modeling, Synthesis and FPGA implementation of flip-flops, registers and counters
  8. Behavioral Modeling, Synthesis and FPGA implementation of Finite State Machines
  9. Case Study – RTL Architecture, Modeling and Verification of a Complete Digital System
  10. Case Study – RTL Architecture Modeling, Synthesis and FPGA Implementation of a Complete Digital System

NB: Scripting exercises with standard tools to be included wherever appropriate.

Recommended Tools: ModelSim, Vivado

Course Objectives

  • To introduce HDL modeling, verification and simulation at RTL abstraction of combinational and sequential subsystems
  • To provide understanding of FPGA Design Flow
  • To provide exposure to different HDL modeling styles and their applications
  • To instill background in assessing the impact of coding styles on synthesis

Course Outcomes (CO)

  • CO1: Able to understand modeling styles
  • CO2: Able to apply modeling styles for realizing digital subsystems
  • CO3: Able to verify and analyze HDL models by writing appropriate test benches
  • CO4: Able to realize RTL models on FPGA platforms and evaluate the impact of coding styles on synthesis
  • CO5: Able to develop RTL architectures for simple digital systems

CO-PO Mapping

CO/PO PO 1 PO 2 PO 3 PSO1 PSO2 PSO3
CO 1 2 3 3 3 2
CO 2 2 3 3 3 2
CO 3 2 3 3 3 2
CO4 2 3 3 3 2
CO5 2 2 3 3 3 2

Reference(s)

  1. Michael D. Ciletti,Advanced Digital Design with Verilog HDL, Second Edition, Pearson Higher Education, 2011.
  2. Morris Mano and Michael D. Ciletti,Digital Design: With an Introduction to the Verilog HDL, Fifth Edition, Pearson Higher Education, 2013.
  3. Stephen Brown and Zvonko Vranesic, Fundamentals of Digital Logic with Verilog Design, Third Edition, McGraw Hill, 2014
  4. Peter Minns and Lan Elliott, FSM Based Digital Design Using Verilog HDL, Fifth Edition, John Wiley and Sons Ltd, 2008.
  5. Parag K. Lala, Principles of Modern Digital Design, Second Edition, John Wiley and Sons Ltd., 2007.

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