Programs
- M. Tech. in Automotive Engineering -Postgraduate
- B. Sc. (Hons.) Biotechnology and Integrated Systems Biology -Undergraduate
Publication Type : Conference Paper
Publisher : IEEE
Source : 2025 8th International Conference on Circuit, Power & Computing Technologies (ICCPCT)
Url : https://doi.org/10.1109/iccpct65132.2025.11176731
Campus : Amritapuri
School : School of Engineering
Center : Humanitarian Technology (HuT) Labs
Department : Electronics and Communication
Year : 2025
Abstract : An FPGA-based digital hearing aid system will enhance the living quality of patients with hearing loss. In this paper, a design and implementation of a digital hearing aid system are discussed, based on FPGA technology, by integrating **machine learning (ML) algorithms** for adaptive scene classification and noise reduction, alongside amplification and DAC conversion, to produce a clearer, enhanced audio signal. The algorithm of ML does classification of the acoustic environment dynamically; examples include quiet, noisy, and speech-dominant classes. Noise reduction filters adapt to every such class for optimal speech clarity. The design methodology to be followed is modular: separate sub-modules for the ADC, ML-based noise reduction, amplification, and DAC processes. This would keep the system scalable, simpler, and easier to debug. The simulation results and the ML-based analysis confirm that the system is effective in both processing and enhancing audio signals through different environments. This research presents a cost-effective, intelligent, and efficient real-time solution to address auditory challenges.
Cite this Research Publication : K Vyshnav Vasudev, Rajesh Kannan Megalingam, A Hybrid FPGA and Machine Learning Framework for Enhancing Hearing Aid Performance, 2025 8th International Conference on Circuit, Power & Computing Technologies (ICCPCT), IEEE, 2025, https://doi.org/10.1109/iccpct65132.2025.11176731