Publication Type : Conference Paper
Publisher : 2018 3rd International Conference on Communication and Electronics Systems (ICCES),
Source : 2018 3rd International Conference on Communication and Electronics Systems (ICCES), IEEE, Coimbatore, India, India (2018)
Url : https://ieeexplore.ieee.org/document/8723989
Campus : Amritapuri
School : School of Engineering
Center : Electronics Communication and Instrumentation Forum (ECIF)
Department : Electronics and Communication
Year : 2018
Abstract : AES (Advanced Encryption Standard) is one of the widely accepted and used algorithms for ensuring the security of data. The advancements in VLSI technology, both from the point of view of design complexity and increase in the probability of error occurrences, have become a significant problem to consider. However, some faults may occur during the implementation of AES which results in reducing the reliability and may cause leakage of information. In this work, we have implemented AES-128 with fault detection techniques based on parity and interleaved parity generation which does not require any additional hardware.
Cite this Research Publication : G. G. Dath, Anu Chalil, and Joseph, J., “An Efficient Fault Detection Scheme for Advanced Encryption Standard”, in 2018 3rd International Conference on Communication and Electronics Systems (ICCES), Coimbatore, India, India, 2018.