Publication Type : Conference Paper
Publisher : IEEE
Source : 2023 IEEE Asia Pacific Conference On Postgraduate Research In Microelectronics And Electronics (PRIMEAsia)
Url : https://doi.org/10.1109/primeasia60757.2023.00026
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2023
Abstract : Approximate multipliers which allow certain level of acceptable error becomes important in many applications such as computer Vision, digital signal processing (DSP), machine learning, and artificial intelligence. This work presents an implementation of an approximate multiplier using a modified Wallace tree design that combines full adders, half adders, and 42 approximate compressors. It uses the PolarFire silicon on chipt (SoC) Icicle Kit FPGA MPFS250_ES and Libero Soc simulation software. The resulting average error percentage is found to be 21.9% along with the reduction in delay by 23.94%.
Cite this Research Publication : Y. Harsha Vardhan, A. Madhumitha, Dhanush P. Kumar, Kirti S. Pande, S Kamatchi, Navin Kumar, Approximate Multiplier for Optimized Power and Delay, 2023 IEEE Asia Pacific Conference On Postgraduate Research In Microelectronics And Electronics (PRIMEAsia), IEEE, 2023, https://doi.org/10.1109/primeasia60757.2023.00026