Publication

Abstract : Increased threats to intellectual property through reverse engineering and SAT attacks have encouraged securing digital circuits using various locking techniques. It is very essential to secure the circuits to avoid replication of circuits without authorization. This paper presents a comparative analysis between SARLock method and IDKLL method of logic locking against SAT attacks. It evaluates the effectiveness of IDKLL based on power consumption, area overhead and delay while increasing the security on attacks like brute force, reverse engineering, and SAT attacks. SARLock utilizes, XNOR and XOR gates to lock the circuit but introduces higher complexity. The IDKLL method uses input-dependent key mechanisms and K-map-based optimizations for logic locking. Performance comparison for the metrics like area, power, delay, and power-delay-product shows that the IDKLL method has more advantages and it is more reliable method for protecting the intellectual property of ICs,