Publication Type:

Journal Article

Source:

International Journal of Electrical, Electronics and Data Communication, Volume 2, Issue 7, p.Online-Ressource (2014)

URL:

http://www.iraj.in/journal/journal_file/journal_pdf/1-67-140419500745-50.pdf

Abstract:

Manufacturing test is a major challenge for very-deep submicron (VDSM) integrated circuits. Mandated productquality levels must be ensured by screening all defective devices before they are shipped. However, defect screening remains a formidable problem, especially for VDSM process technologies, since it is impossible to explicitly target every possible defect. This paper mainly deals with a method to generate N-detect test sets that provide high defect coverage making
judicious use of new pattern quality metrics which is basically depended on the concept of ZDD. Simulation results for benchmark circuits show that, this method provides higher fault coverage and coverage ramp-up compared to other methods using BDD as ZDD provides an efficient way of solving problems expressed in terms of set theory and cube vectors.

Cite this Research Publication

B. D. Kumar Reddy and Mohan, N., “N-Detect Test Pattern Generation And Relaxation Using ZDD”, International Journal of Electrical, Electronics and Data Communication, vol. 2, no. 7, p. Online-Ressource, 2014.

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