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Publication Type : Conference Paper
Publisher : Proceedings of the 2019 IEEE International Conference on Communication and Signal Processing, ICCSP 2019
Source : Proceedings of the 2019 IEEE International Conference on Communication and Signal Processing, ICCSP 2019, Institute of Electrical and Electronics Engineers Inc., p.730-734 (2019)
ISBN : 9781538675953
Keywords : Advanced Encryption Standard, Cryptography, Data Encryption Standard, Data privacy, Digital storage, Figure of merit (FOM), Maximum distance, Processing elements, Signal processing, Systolic, Systolic arrays
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2019
This paper construes systolic array based architecture for the implementation of mix column and inverse mix column layers of AES block cipher algorithm. Mix column layer oriented processing units (PEs) that relies on Galois field operations drives the platform for the systolic arrays. Usage of systolic approach for mix column provides better through- put implementations. Inference of high throughput for systolic architecture were obtained on comparing FOM computed for the systolic architecture implementation against conventional hardware implementations. © 2019 IEEE.
Cite this Research Publication : S. M., K. N. Sreehari, and R., B., “Systolic array implementation of mix column and inverse mix column of AES”, in Proceedings of the 2019 IEEE International Conference on Communication and Signal Processing, ICCSP 2019, 2019, pp. 730-734.