Publication Type : Journal Article
Publisher : Inderscience Enterprises Ltd
Source : International Journal of High Performance Systems Architecture, Inderscience Enterprises Ltd., Volume 6, Number 1, p.51-60 (2016)
Url : https://www.scopus.com/inward/record.uri?eid=2-s2.0-84969674382&partnerID=40&md5=76b4054cf29462c6cbf77e3270961bfd
Keywords : Algorithms, Binary decision diagrams, Bins, Boolean functions, Decision diagram, Decision theory, Multiple faults, Test pattern generations, Test power reduction, Testing, ZBDDs
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Year : 2016
Abstract : An algorithm of test pattern generation for multiple faults is proposed using the zero suppressed decision diagrams (ZBDDs). Test pattern generation plays a major role in the design and testing of any chip. The proposed ZBDD is generated from its corresponding binary decision diagram (BDD). A test ZBDD is obtained from the true and faulty ZBDDs and the test patterns are generated from the test ZBDD. The obtained patterns are reordered because the order in which these patterns are used to test the chip is immaterial as far as the faults are concerned but the transitions between the test patterns affect the test power. Hence, the primary objective of the proposed work is the generation of test patterns for a given set of multiple faults. The next objective is to reduce the test power which is the power consumed during testing. © 2016 Inderscience Enterprises Ltd.
Cite this Research Publication : Dr. Anita J. P. and Sudheesh, P., “Test power reduction and test pattern generation for multiple faults using zero suppressed decision diagrams”, International Journal of High Performance Systems Architecture, vol. 6, pp. 51-60, 2016.