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Vedic-optimized RISC-V processor design

Publication Type : Conference Paper

Publisher : IEEE

Source : 2025 8th International Conference on Circuit, Power & Computing Technologies (ICCPCT)

Url : https://doi.org/10.1109/iccpct65132.2025.11176495

Campus : Amritapuri

School : School of Engineering

Center : Humanitarian Technology (HuT) Labs

Department : Electronics and Communication

Year : 2025

Abstract : This research paper is about designing and implementation of the an Vedic-optimized ALU(Arithmetic logic unit) for a risc-v processor to enhance computational efficiency. The RISC-V instruction set architecture (ISA) was chosen because it is open-source and modular in design, making it easy to integrate innovative components. The ALU uses here the brent kung adder and Vedic multiplier, which reduces the latency and power consumption by significant percent compared to ripple carry adder method or other multipliers.

Cite this Research Publication : Tamminaina Siva Kumar, Rajesh Kannan Megalingam, Vedic-optimized RISC-V processor design, 2025 8th International Conference on Circuit, Power & Computing Technologies (ICCPCT), IEEE, 2025, https://doi.org/10.1109/iccpct65132.2025.11176495

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