Publication

Abstract : There has been a significant boom in the consumer electronics industry and the DSP cores have become more inte-grated into such consumer electronic appliances for efficient pro-cessing. One of the popularly used DSP algorithm is the Discrete Cosine Transform (DCT) which has wide-ranging applications include encoding, decoding, video/audio processing, and analog-to-digital conversion, especially in HDTV chips. This paper presents a novel technique for safeguarding DCT Intellectual Property (IP) in sequential circuits via watermarking. It utilizes a Finite State Machine (FSM) steered by a Cellular Automaton (CA) to implement the watermarking mechanism. A UART receiver, written in Verilog and deployed on an FPGA, retrieves keys from a Putty terminal, managing FSM state transitions and overseeing the decryption process of the sequential circuit. This method results in a 15 % reduction in power consumption and a 23 % decrease in delay, although it incurs an 18 % increase in area utilization. This strategy provides a robust solution for IP protection in digital circuit design, showcasing practical implementation and performance enhancements. The strength analysis reveals a probability of coincidence (Pc) of Pc =29.3897x 10–40 and a false positive rate (fc) of 2.98x 10-38.