Publication

Abstract : The increasing vulnerability of memory devices to errors due to smaller transistor sizes, larger densities, and lower operating voltages raises the demand for efficient Error Correcting Codes (ECC) in memory systems in contemporary applications. Effective ECCs are essential for preserving system dependability and data integrity, particularly in mission-critical applications including data centers, aircraft, medical equipment, and automotive systems. ECCs have dramatically improved data integrity and system reliability across fields such as telecommunications, cloud computing, and automotive technology. The “Row-Wise Hamming” leverages an optimized row-wise encoding and decoding mechanism that significantly reduces redundancy. In comparison to current ECC systems, the proposed Row-wise Hamming coding methodology optimizes memory dependability by reducing power consumption, area, and maximum delay by 40 %. The results from experiments establish the superior computational overhead performance of Row-Wise Hamming ECC, hence establishing it as a highly favorable solution for modern memory dependability issues.