Publication Type : Conference Paper
Publisher : IEEE
Source : 2025 8th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)
Url : https://doi.org/10.1109/iementech65115.2025.10959548
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2025
Abstract : Dynamic comparators are essential for enabling the fast and accurate performance needed by analog-to-digital converters (ADCs) in today's communication systems. However, conventional designs often suffer from performance degradation at low input difference voltages and significant delay variations under temperature fluctuations, which many designers tend to ignore. This paper proposes an improved dynamic comparator design that addresses these challenges by integrating a cascode cross-coupled configuration within the pre-amplifier section to enhance gain and ensure reliable operation at small input differences. Additionally, a temperature compensation circuit is introduced at the latch stage to mitigate the impact of temperature variations on delay. In the proposed dynamic comparator, the i) propagation delay is decreased by 35.51% and 58.21%, and the ii) delay variation at different temperatures is decreased by 36.17% and 68.22% in comparison with the re-implemented cascode cross-coupled dynamic comparator and conventional dynamic comparator, respectively.
Cite this Research Publication : Pala Lakshman Sai, V Surya Prathik, M Roopa Rajan, Kirti S. Pande, Delay-Optimized High-Speed Dynamic Comparator with Temperature Compensation, 2025 8th International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech), IEEE, 2025, https://doi.org/10.1109/iementech65115.2025.10959548