Publication

Abstract : A reconfigurable 16KB cache memory system is designed using Verilog Hardware Description Language to support multiple cache mapping techniques, including direct-mapped and set-associative organizations. The set-associative architecture is configurable as two-way, four-way, or eight-way, offering flexibility in terms of associativity and performance. A mode-selectable control mechanism enables dynamic switching between cache architectures during runtime, based on application-specific requirements or performance trade-offs. The design utilizes Block RAM (BRAM) inference for efficient FPGA implementation, supporting selective activation of cache blocks to optimize access time and minimize power consumption by deactivating unused sets. The modular and parameterized structure makes it highly scalable and well-suited for implementation in embedded processors, FPGA-based accelerators with limited resources, and customizable computing platforms. The proposed cache architecture is novel because it allows dynamic runtime reconfiguration between direct-mapped and multiple set-associative cache structures, which is rarely implemented in FPGA-based designs.