Publication

Abstract : Modern processors improve execution speed through instruction pipelining, through steps like fetch, decode, execute, memory and write-back run at the same time. This concurrency of tasks greatly increases throughput, but it also creates hazards, including data and control dependencies, that can slow down execution. A common way to manage these hazards is stalling, which maintains correctness but lower efficiency by increasing cycle counts. In this work, the design and implementation of a five-stage pipelined processor simulator developed in C++ are presented. The simulator models instruction-level parallelism and includes two important techniques: forwarding and branch prediction. Forwarding reduces unnecessary stalls by providing intermediate results directly from the execution stage to dependent instructions. Branch prediction deals with control hazards by guessing and fetching instructions. When predictions are incorrect, the simulator discards the wrong instructions and continues in a correct sequence. These mechanisms allow the simulator to show a more accurate representation of the behavior of modern processors and demonstrate the effectiveness of strategies to reduce hazards and improve performance.