Publication

Abstract : The growing need for energy-efficient computing and fast arithmetic operations has renewed interest in reversible logic systems, especially for designing arithmetic units like adders and subtractors. Traditional digital logic circuits lose information during computation, which causes power loss. This issue is particularly important in low-power and quantum-aware systems. Reversible computing provides a strong solution by preventing information loss through one-to-one input-output mappings. This paper discusses a Python-based implementation of a new reversible carry look-ahead Binary-Coded Decimal (BCD) subtractor. The subtractor architecture includes a nine’s complementer, a carry look-ahead BCD adder, and a fast parallel adder, which are all modeled using basic reversible gates like Toffoli, Fredkin, and Peres gates. By simulating the logical behavior of reversible components in Python, the design avoids the complexity of hardware synthesis while ensuring high accuracy in logic validation.Importantly, the subtractor can handle double-digit BCD numbers, making it function as an 8-bit subtractor. Each decimal digit is encoded using 4 bits according to the BCD standard. This setup allows the system to process 8-bit inputs for both the minuend and subtrahend, enabling subtraction of decimal values from 00 to 99. This improves the practical relevance of the model and brings the implementation closer to real-world applications where multi-digit arithmetic is common.This implementation connects the gap between theoretical reversible logic design and its use in power-conscious computing as well as quantum logic research. The proposed work also acts as an educational tool, allowing students and early researchers to explore reversible logic concepts without needing FPGA platforms or HDL tools, paving the way for future integration into hardware and quantum computing platforms.