Publication

Abstract : This paper introduces a 32-operand floating-point adder operating at high speed, integrating a multi-level Carry-Save Adder (CSA) with the optimized Wallace Tree architecture to enhance multi-operand summation while being IEEE-754 compliant. Software simulations using 32 randomly generated operands (-100 to +100) produce almost a 50% decrease in execution time versus traditional sequential pairwise addition, emphasizing the virtues of reduction parallelism strategies. Although hardware parameters like area, power, and frequency weren't quantified, the architecture has a strong potential for integration within FPGA/ASIC accelerators, AI processors, digital signal processors, and other high-throughput computing devices. The design here explains how integrating CSA and Wallace Tree approaches can be effective in terms of floating-point addition performance and presents a scalable architecture for high-performance arithmetic designs.