Publication Type : Journal Article
Publisher : Proceedings of the National Academy of Sciences, India Section A: Physical Sciences
Source : Proceedings of the National Academy of Sciences, India Section A: Physical Sciences, Volume 89, Issue 2, p.257–268 (2019)
Url : https://doi.org/10.1007/s40010-017-0464-4
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Year : 2019
Abstract :
Vedic mathematics is the ancient Indian method of mathematics based on 16 Sutras applicable to various branches of mathematics like trigonometry, calculus, geometry, conics etc. Multiplication is effectively used in modern communication and Digital Signal Processing applications. Ordinary multiplication requires propagation of carry from LSB to MSB while adding binary partial products, which limits the overall speed of multiplication. Vedic mathematics helps in generation of partial products and sums in one step, and ensures reduction in overall propagation delay. Urdhva Tiryakbhyam Sutra and Nikhilam Sutra are the two multiplication techniques used in Vedic mathematics. In this paper, an 8 * 8 Nikhilam Sutra multiplier for three different sets of bases is realized. The concepts of Urdhva Tiryakbhyam Sutra multiplication are used for the implementation of the proposed multiplier. The implementation results are compared with that of a Modified Booth's multiplier in terms of delay, area and power. The design is synthesized in Synopsys Design Compiler using CMOS 90 nm technology, and results show that the proposed multiplier using Nikhilam Sutra with 25 bases is faster than the Modified Booth's multiplier by 51.28%.
Cite this Research Publication : Prabhu E., Mangalam, H., and Gokul, P. R., “A Delay Efficient Vedic Multiplier”, Proceedings of the National Academy of Sciences, India Section A: Physical Sciences, vol. 89, no. 2, pp. 257–268, 2019.