Publication Type : Journal Article
Publisher : Advances in Intelligent Systems and Computing
Source : Advances in Intelligent Systems and Computing, Springer Verlag, Volume 394, p.273-284 (2016)
Url : http://www.scopus.com/inward/record.url?eid=2-s2.0-84959097688&partnerID=40&md5=203ac9b2c824df22de0e10444c75df98
ISBN : 9788132226543
Keywords : 90 nm technology, Accumulator, Adders, Artificial intelligence, Computer programming, ce, Input and outputs, Propagation delays, Sizing strategy, Standard cell
Campus : Amritapuri
School : Department of Computer Science and Engineering
Department : Computer Science
Year : 2016
Abstract : This paper describes the characteristics and analysis of accumulator which are obtained from simulations performed in Cadence (Virtuoso) and done the layout. The sizing strategy used for sizing the standard cell blocks used to build the accumulator result in a minimum propagation delay between input and output. © Springer India 2016.
Cite this Research Publication : N. C. Balan and Jose, A. A., “Accumulator design in cadence 90 nm technology”, Advances in Intelligent Systems and Computing, vol. 394, pp. 273-284, 2016.