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Publication Type : Journal Article
Publisher : Journal of Central South University, Central South University of Technology
Source : Journal of Central South University, Central South University of Technology, Volume 23, Number 7, p.1669-1681 (2016)
Keywords : Architecture, Booth multipliers, decimation in time, Digital arithmetic, Electron multipliers, Existing systems, Fast Fourier transforms, Field programmable gate arrays (FPGA), Floating points, integrated circuit design, Proposed architectures, Radix-4 fft butterflies, Reconfigurable hardware, Reduced power consumption, Reusability, Switching activities
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Year : 2016
Abstract : In this work, power efficient butterfly unit based FFT architecture is presented. The butterfly unit is designed using floating-point fused arithmetic units. The fused arithmetic units include two-term dot product unit and add-subtract unit. In these arithmetic units, operations are performed over complex data values. A modified fused floating-point two-term dot product and an enhanced model for the Radix-4 FFT butterfly unit are proposed. The modified fused two-term dot product is designed using Radix-16 booth multiplier. Radix-16 booth multiplier will reduce the switching activities compared to Radix-8 booth multiplier in existing system and also will reduce the area required. The proposed architecture is implemented efficiently for Radix-4 decimation in time (DIT) FFT butterfly with the two floating-point fused arithmetic units. The proposed enhanced architecture is synthesized, implemented, placed and routed on a FPGA device using Xilinx ISE tool. It is observed that the Radix-4 DIT fused floating-point FFT butterfly requires 50.17% less space and 12.16% reduced power compared to the existing methods and the proposed enhanced model requires 49.82% less space on the FPGA device compared to the proposed design. Also, reduced power consumption is addressed by utilizing the reusability technique, which results in 11.42% of power reduction of the enhanced model compared to the proposed design.
Cite this Research Publication : Prabhu E., Mangalam, H., and Karthick, S., “Design of area and power efficient Radix-4 DIT FFT butterfly unit using floating point fused arithmetic”, Journal of Central South University, vol. 23, pp. 1669-1681, 2016.