Publication

Abstract :

The k-Nearest Neighbor (k-NN) algorithm is widely utilized for classification tasks in machine learning due to its inherent simplicity and effective performance. However, achieving high accuracy in hardware implementations of k-NN poses significant challenges, particularly related to the computational demands of distance calculations across various datasets. This paper presents an implementation of the k-NN algorithm on a Field-Programmable Gate Array (FPGA) using Verilog Hardware Description Language (HDL), employing the Manhattan distance metric to enhance computational efficiency. The proposed design supports multiple classes and is validated through simulations using various datasets, ensuring precise classification by identifying the closest matches based on the input data attributes. Optimized for FPGA-based hardware acceleration, our solution enables real-time classification by efficiently processing absolute differences in coordinates while minimizing resource utilization. The resulting implementation of algorithm in Basys3 FPGA Board provides high-speed, efficient k-NN classification that is well-suited for real-time embedded systems applications, with a scalable design capable of accommodating datasets of varying complexities.