Publication Type:

Conference Paper

Source:

Proceedings of the Second International Conference on Computer and Communication Technologies: IC3T 2015, Volume 1, Springer India, New Delhi, p.187–194 (2016)

ISBN:

9788132225171

URL:

http://dx.doi.org/10.1007/978-81-322-2517-1_19

Abstract:

Modern Network Intrusion detection needs a high-speed interface to analyze the incoming packet. Several network intrusion detection applications detect multiple strings in the payload of a packet by comparing it against predefined pattern set which requires more memory and computation power. To meet this, a dedicated hardware with high processing capacity can be placed at the port of incoming packets. Field Programmable Gate Array (FPGA) is the choice as it can be programmed easily and dynamically for parallel computing. Moreover, FPGA devices support at high-speed interface and are capable of providing better processing capability than other device; also it can be reprogrammed when it is needed. This paper proposes a new alternative approach to leaf attaching algorithm to improve the memory efficiency of algorithm.

Cite this Research Publication

S. Anuraj, Premalatha, P., and Dr. Gireesh K. T., “High Speed Network Intrusion Detection System Using FPGA”, in Proceedings of the Second International Conference on Computer and Communication Technologies: IC3T 2015, Volume 1, New Delhi, 2016, pp. 187–194.

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