Publication Type : Conference Paper
Publisher : 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS)
Source : 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), IEEE, Bhopal, India (2017)
Url : https://ieeexplore.ieee.org/document/8293933
Keywords : Transistors, SRAM cells, Leakage currents, Circuit stability, Threshold voltage, Inverters
Campus : Bengaluru
School : School of Engineering
Center : Electronics Communication and Instrumentation Forum (ECIF)
Department : Electronics and Communication
Year : 2017
Abstract : During recent years SRAM has become the topic of crucial research due to increased demand in mobile applications. For low power applications, leakage reduction is very important. This brings the incentive to design low leakage SRAM cells. In this work, a Dynamic Threshold 8T (DT8T) SRAM cell is proposed to elevate the performance in terms of maintaining stability and leakage reduction by using variable threshold voltage transistors. During write and hold mode, drivability of transistors is improved with forward body biasing. For reducing the leakage current, reverse body biasing is used during read mode of operation. The proposed circuit is designed in 45 nm CMOS technology and is simulated using Cadence Virtuoso platform. At supply voltage of 0.5 V, read leakage currents through feedback transistors are observed as 0.261 pA and 0.198 pA when body is reverse biased at 0.6 V and these are reduced by approximately 84% compared to D8T SRAM cell. This proposed SRAM cell draws 7.31 nA leakage current in standby mode which is 24% lesser compared to conventional 6T SRAM cell.
Cite this Research Publication : R. Suthar, Pande, K. S., and Murty, N. S., “Leakage Reduction in DT8T SRAM Cell Using Body Biasing Technique”, in 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS), Bhopal, India, 2017.