Publication Type : Conference Paper
Publisher : Procedia Computer Science
Source : Procedia Computer Science, Elsevier B.V., Volume 115, p.174-181 (2017)
Url : https://www.scopus.com/inward/record.uri?eid=2-s2.0-85032439886&doi=10.1016%2fj.procs.2017.09.123&partnerID=40&md5=58dcaa6b75bb83e1349b281bd4867850
Keywords : Back doors, Design for testability, LFSR, Linear feedback shift registers, Personal computing, Power overhead, Scan chain, Scan designs, Sensitive informations, Shift registers, Side channel attack, Testability
Campus : Coimbatore
School : Department of Electronics and Communication Engineering
Department : Electronics and Communication
Year : 2017
Abstract : Security and testability are the most important factors affecting designing for testability. Scan chain based testing is a standard DfT (Design for Testability) due to its simple design and low cost. But this method can act as back door, through which the hacker can retrieve the sensitive information through side channel attack. Therefore we developed an efficient and inexpensive LFSR (linear feedback shift register) based secured architecture through which it provides predominant security without effecting testability. The experimental result leads to a low area and power overhead with a secure methodology. © 2017 The Author(s).
Cite this Research Publication : M. I. Shiny and M. Devi, N., “LFSR Based Secured Scan design Testability Techniques”, in Procedia Computer Science, 2017, vol. 115, pp. 174-181.