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Publication Type : Conference Paper
Publisher : 2017 International conference on Microelectronic Devices, Circuits and Systems
Source : 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS) (2017)
Keywords : Arbiter, asynchronous circuits, baseline router, crossbar switch fabric, high performance computing, intellectual property cores, interconnection links, IP cores, many-multicore processor architectures, MARX microarchitecture, MAS microarchitecture, merged arbiter-multiplexer microarchitecture, microarchitecture, Microprocessor chips, Multiplexing, Multiprocessing systems, Network routing, Network-on-chip, network-on-chip router, Parallel processing, pipeline processing, pipelined merged arbitration-switching microarchitecture, Pipelining, PMAS microarchitecture, Ports (Computers), Power Consumption, router, routing, routing computation logic, scalable communication framework, Switch fabric, Switches, switching functionalities, switching techniques, Throughput, wave-pipelining, Wave-pipelining and Network on Chip, WMAS microarchitecture, wormhole NoC router
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Verified : No
Year : 2017
Abstract : In Many/Multi-core processor architectures, hundreds and thousands of Intellectual Property (IP) cores are integrated to reinforce parallel processing and high performance computing. Integration of IP cores is effectively realized by a scalable communication framework, Network on Chip (NoC). NoC comprises of routers and interconnection links which aid transfer of information between IP cores. It is the router which dominants the performance of NoC. A baseline router incorporates the FIFO (First In First Out) buffers, the routing computation logic, the arbiter and the crossbar switch fabric. In this paper, we propose different techniques of merging arbitration and switching functionalities accomplished in wormhole NoC router. Proposed microarchitectures for merging these functionalities are Merged Arbitration and Switching (MAS) microarchitecture based on multiplexer reorganization, Pipelined Merged Arbitration and Switching (PMAS) microarchitecture based on Pipelining and Wave-pipelined Merged Arbitration and Switching (WMAS) microarchitecture based on Wave-pipelining. Synthesis results show that the MAS microarchitecture outperforms the Merged ARbiter and multipleXer (MARX) microarchitecture in area and power consumption by 21.8% and 39.5% respectively. Simulation results show that the PMAS and WMAS microarchitectures outperform MARX microarchitecture in throughput by 40% and 60% respectively at a marginal cost of area and power consumption. Therefore, the benefits of using MAS microarchitecture in wormhole NoC router is low area and power consumption and PMAS or WMAS microarchitecture is high throughput.
Cite this Research Publication : M. Vinodhini and Dr. N.S. Murty, “Merged arbitration and switching techniques for network on chip router”, in 2017 International conference on Microelectronic Devices, Circuits and Systems (ICMDCS), 2017.