Publication Type : Conference Paper
Publisher : TechSym 2011 - Proceedings of the 2011 IEEE Students' Technology Symposium,
Source : TechSym 2011 - Proceedings of the 2011 IEEE Students' Technology Symposium, Kharagpur, p.204-210 (2011)
Url : http://www.scopus.com/inward/record.url?eid=2-s2.0-79959458074&partnerID=40&md5=f1f426a324f1e03539a230a266b5b93d
ISBN : 9781424489428
Keywords : Algorithms, Application specific integrated circuits, Block ciphers, Communication systems, Computer architecture, Computer hardware, Computer hardware description languages, Computing techniques, Cryptographic algorithms, Cryptographic applications, Cryptography, Data paths, General purpose computers, General purpose processors, Growing demand, Hardware, Hardware design, Modelsim, Network architecture, Re-configurable, Real time control, Real-time implementations, Reconfigurable hardware, Reconfigurable processors, Research papers, Rijndael, Synopsys, Verilog HDL
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Year : 2011
In today's world there is a growing demand for real-time implementation of cryptographic algorithms which are being used in secure communication systems, networks and security systems. Traditional computing techniques involved the use of application specific integrated circuits to achieve high performance but with extremely inflexible hardware design meanwhile the flexibility of hardware design was achieved at the cost of slow processing by using general purpose processors. In this research paper a novel reconfigurable processor architecture has been presented for cryptographic applications that bridges the above mentioned gap and also sustains implementations that can show equal or even better performance results than custom-hardware and hitherto preserves all the flexibility of general-purpose processors. We present implementations for representative algorithms of block cipher such as Rijndael, RC5 and RC6 on our architecture. The RTL Description is done in ModelSim using Verilog HDL and the results are synthesized in Synopsys. This work presents an emerging reconfigurable hardware that potentially delivers flexible high performance for cryptographic algorithms. © 2011 IEEE.
Cite this Research Publication : Rajesh Kannan Megalingam, Joseph, I. P., Gautham, P., Parthasarathy, R., Deepu, K. B., and M. Nair, M., “Reconfigurable Cryptographic Processor for multiple Crypto - Algorithms”, in TechSym 2011 - Proceedings of the 2011 IEEE Students' Technology Symposium, Kharagpur, 2011, pp. 204-210.