Publication Type : Journal Article
Publisher : IEEE Access, IEEE Institute of Electrical and Electronics Engineers
Source : IEEE Access, IEEE Institute of Electrical and Electronics Engineers,
Url : https://ieeexplore.ieee.org/abstract/document/9203819
Campus : Bengaluru
School : School of Engineering
Department : Electronics and Communication
Year : 2020
Abstract : Ensuring reliable data transmission in multicore System on Chip (SoC), which employs Network on Chip (NoC), is a challenging task. This task is well addressed by Error Correcting Codes (ECC) in on-chip as well as off-chip networks. ECC significantly improves reliability of NoC interconnects with area and power overhead. In this paper, we propose a novel Transient Error Correction (TEC) coding scheme for reliable low power data link layer in NoC to attain a high error correction capability with less hardware overhead. Performance of TEC scheme is evaluated with realistic traffic patterns and validated with simulation results. The proposed scheme has less residual errors than the Hamming product code enabling reliable transmission at lower link swing voltage. Further, the scheme reduces the power consumption of NoC interconnects up to 71% as compared to Hamming product code with a marginal increase in codec delay and thus router delay. TEC scheme performs well in high noise environment with no delay penalty associated with retransmission.
Cite this Research Publication : M. Vinodhini, N. S. Murty, and Dr. T. K. Ramesh, “Transient Error Correction Coding Scheme for Reliable Low Power Data Link Layer in NoC”, IEEE Access, vol. 8, pp. 174614-174628, 2020.