Publication Type : Conference Proceedings
Publisher : Springer Berlin Heidelberg
Source : Communications in Computer and Information Science
Url : https://doi.org/10.1007/978-3-642-22709-7_18
Campus : Nagercoil
School : School of Computing
Year : 2011
Abstract : Continuous effort to achieve higher performance without driving up the power consumption and thermal effects has led the researchers to look for alternative architectures for microprocessors. Like the parallel processing which is extensively used in today’s all microprocessors, multi-core architecture which combines several independent microprocessor cores in a single die has currently become very popular in most high performance integrated circuits. Although multi-core processor offers excellent instruction execution speed with reduced power consumption, optimizing performance of individual processors and then incorporating them by interconnection on a single chip is a non-trivial task. This paper investigates the leading challenges associated with current high performance multi-core processor in terms of different types of power optimization techniques.
Cite this Research Publication : A. S. Radhamani, E. Baburaj, Research on Power Optimization Techniques for Multi Core Architectures, Communications in Computer and Information Science, Springer Berlin Heidelberg, 2011, https://doi.org/10.1007/978-3-642-22709-7_18