Publication

Abstract : In modern processor architectures, the Arithmetic Logic Unit (ALU) serves as a fundamental component responsible for executing arithmetic and logical operations. Multiplication, being a computationally intensive task within the ALU, greatly influences overall performance. This paper proposes an enhanced ALU architecture that integrates a high-speed Vedic multiplier based on the Urdhva Tiryagbhyam sutra. This multiplier offers a parallel and efficient approach to computation, reducing propagation delay and improving operational speed. The proposed design is implemented and simulated using Python on Jupyter Notebook, demonstrating significant improvements in area and timing compared to conventional multiplier-based ALUs. The results affirm that Vedic mathematics, when applied to digital design, offers a promising alternative for efficient hardware computation.