Year : 2025
Performance analysis of 4:1 MUX APUF Architecture Implemented on Zynq 7000 SoC FPGA
Cite this Research Publication : Kaveri Hatti, C. Paramasivam, Performance analysis of 4:1 MUX APUF Architecture Implemented on Zynq 7000 SoC FPGA, Integration, Elsevier BV, 2025, https://doi.org/10.1016/j.vlsi.2025.102379
Publisher : Elsevier BV
Year : 2021
Design of Efficient Low Power Strong PUF for Security Applications
Cite this Research Publication : Akash B Patel, S. Kamatchi, Kaveri Hatti “Design of Efficient Low Power Strong PUF for Security Applications”, ICOSEC 2021 IEEE Conference, which held from 7-9, October 2021 at Kongunadu College of Engineering and Technology, Tamil Nadu, India
Publisher : IEEE
Year : 2020
Design and Implementation of Enhanced PUF Architecture on FPGA
Cite this Research Publication : Kaveri Hatti, C Paramasivam, Design and Implementation of Enhanced PUF Architecture onFPGA, International Journal of Electronics Letters, Informa UK Limited, 2020, https://doi.org/10.1080/21681724.2020.1859141
Publisher : Informa UK Limited