Qualification: 
M.Tech, B-Tech
sreeharikn@am.amrita.edu

Sreehari K. N. currently serves as Assistant Professor (Senior Grade) at the Department of Electronics and Communication Engineering, School of Engineering, Amrita Vishwa Vidyapeetham, Amritapuri campus. He has completed  B. Tech. in Electronics and communication Engineering from Calicut university and  M. Tech. in VLSI design from Amrita Vishwa Vidyapeetham. He is currently pursuing Ph.D at Amrita Vishwa Vidyapeetham

His research areas include Hardware security, VLSI design and Embedded system . He has 8 years of teaching experience at Amrita Vishwa Vidyapeetham

Qualification

  • Ph. D.: On-going
  • M. Tech. : VLSI Design
    Amrita School of Engineering, Amritapuri camps
  • B. Tech. : Electronics and Communication Engineering
    Calicut university

Publications

Publication Type: Conference Paper

Year of Publication Title

2020

Nirmal Vinod, K. V. Abhishek Neelakandan, R. Udith, K. Sayooj Devadas, K. Dinesh, Anu Chalil, and K. N. Sreehari, “Performance Evaluation of LUTs in FPGA in Different Circuit Topologies”, in 2020 International Conference on Communication and Signal Processing (ICCSP), Chennai, India, India, 2020.[Abstract]


Field Programmable Gate Arrays (FPGAs) are the most important device in the field of electronics industry. FPGAs are pre-manufactured chips which could be modified electrically, to turn out to be practically any sort of advanced circuit or frame-work. The highlighting part of FPGA is its architecture which gives a broad idea about their programmable logic functionalities and interconnects. The programmable logic functions can be implemented through logic blocks that can be programmed. The Logic Block contains storage elements, multiplexers, and Look Up Table (LUT). The final device's performance and other characteristics are governed by the quality and condition of the architecture of FPGA as well as its elements. In this project, we design the LUT architecture using different circuit topologies to obtain the smallest Power delay product (PDP) value.

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2020

V. Akshaya, K. N. Sreehari, and Anu Chalil, “VLSI Implementation of Turbo Coder for LTE using Verilog HDL”, in 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC), Erode, India, India, 2020.[Abstract]


Turbo codes are error correction codes that are widely used in communication systems. Turbo codes exhibits high error correction capability as compared with other error correction codes. This paper proposes a Very Large Scale Integration (VLSI) architecture for the implementation of Turbo decoder. Soft-in-soft out decoders, interleavers and deinterleavers is used in the decoder side which employs Maximum-a-Posteriori (MAP) algorithm. The number of iterations required to decode the information bits being transmitted is reduced by the use of MAP algorithm. For the encoder part, this paper uses a system which contains two Recursive convolutional encoders along with pseudorandom interleaver in encoder side. The Turbo encoding and decoding is done using Octave, Xilinx Vivado, Cadence tools. The system is implemented and synthesized in Application Specific Integrated Circuit (ASIC).Timing analysis has been done and GDSII file has been generated.

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2019

Sasikumar M., K. N. Sreehari, and Bhakthavatchalu R., “Systolic array implementation of mix column and inverse mix column of AES”, in Proceedings of the 2019 IEEE International Conference on Communication and Signal Processing, ICCSP 2019, 2019, pp. 730-734.[Abstract]


This paper construes systolic array based architecture for the implementation of mix column and inverse mix column layers of AES block cipher algorithm. Mix column layer oriented processing units (PEs) that relies on Galois field operations drives the platform for the systolic arrays. Usage of systolic approach for mix column provides better through- put implementations. Inference of high throughput for systolic architecture were obtained on comparing FOM computed for the systolic architecture implementation against conventional hardware implementations. © 2019 IEEE.

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2018

K. N. Sreehari, “Efficient key management methods for symmetric cryptographic algorithm”, in 2018 IEEE International Conference on Computational Intelligence and Computing Research (ICCIC), 2018.[Abstract]


Key management is major issue in cryptographic algorithms. Key management includes key generation and sharing of secret key between sender and the receiver. The generated key should be random in nature. The sharing of key through secure channel is also a major research area. In this paper, different key generation methods are considered for a symmetric algorithm. In the first method, lfsr based key is used. In the second method, hash function method is used for key generation. The cryptographic system with above key generation techniques is modelled using hardware description language using VIVADO software.

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2018

K. N. Sreehari and Bhakthavatchalu R., “Implementation of hybrid cryptosystem using DES and MD5”, in 2018 3rd International Conference on Communication and Electronics Systems (ICCES), 2018.[Abstract]


Cryptographic techniques offers authenticity, Integrity and secrecy during data transmission. In this paper, a hybrid cryptosystem, which uses both symmetric crypto algorithm and hashing techniques, is proposed. The hash value of message is calculated using MD5 algorithm. The same message is encrypted using double DES algorithm using secret keys. The ciphertext produced from double DES and hash value are combined and transmitted. At the receiver side, the ciphertext is separated from hash value and decrypted to get original message. The hash value of decrypted message is calculated at receiver side also using MD5 algorithm. This hash value is compared with hash value received from sender to check data integrity.

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Publication Type: Conference Proceedings

Year of Publication Title

2020

Syam Krishnan T., Anu Chalil, and K. N. Sreehari, “VLSI Implementation of Reed Solomon Codes”, 2020 Fourth International Conference on Computing Methodologies and Communication (ICCMC). pp. 280-284, 2020.[Abstract]


Reed Solomon(RS) codes are error correction codes that are widely used in communication systems. RS codes exhibits high error correction capability as compared with other error correction codes. Encoding is the process of adding parity bits to the input messages. The input message and parity bit together form the codeword. The input of the decoder can contain errors. In decoding, the original message is retrieved by applying different algorithms to the codeword. This paper uses LFSR for encoding and the Peterson Gorenstein Zierler algorithm for decoding. This work is aimed at execution of RS codes using different technologies. The Reed Solomon encoding and decoding is done using Octave, Vivado, Cadence tools. The data is tested for a single error and two errors. The system is implemented and synthesized in Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA). Timing analysis has been done and GDSII file has been generated.

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Faculty Research Interest: