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Implementation of Optimized VLSI Architecture for Montgomery Multiplication Algorithm

Publication Type : Conference Paper

Publisher : IEEE

Source : In Information and Communication Technology for Competitive Strategies (ICTCS 2020) Intelligent Strategies for ICT (pp. 277-285). Springer Singapore.

Url : https://link.springer.com/chapter/10.1007/978-981-16-0882-7_23

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2021

Abstract : Montgomery multiplication algorithm is widely used in many cryptographic algorithms to provide secure communication between the transmitter and receiver. The main objective of this paper is to study the potential gains of Montgomery algorithm compared to classic ones, For the speedy operation, Montgomery modular multiplication algorithm employs carry–save addition to reduce the carry propagation time at each cycle of addition, but it will increase the hardware complexity. Using carry–save adder as standard, carry–select, carry–skip adders are considered with different optimized hardware versions and thus increases the performance. Simulation is done by using Xilinx design 14.2. The pro-posed Montgomery algorithm design is then compared with the classic one in terms of power, area, delay and thus can achieve improved performance and speed when compared to the classic Montgomery multiplier.

Cite this Research Publication : Thomas, A., Chalil, A. and Sreehari, K.N., 2021. Implementation of Optimized VLSI Architecture for Montgomery Multiplication Algorithm. In Information and Communication Technology for Competitive Strategies (ICTCS 2020) Intelligent Strategies for ICT (pp. 277-285). Springer Singapore.

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