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Scalable and Rapid Fault Detection of Memories Using MBIST and Signature Analysis

Publication Type : Conference Paper

Publisher : Elsevier

Source : Lecture Notes in Electrical EngineeringVolume 703, Pages 351 - 3672021 International Conference on Signal and Data Processing, ICSDP 2019

Url :

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2019

Abstract : A novice scalable MBIT unit with MISR signature analysis is proposed in this project. Enhancement of MBIST architecture with signature analysis significantly improvises resolution of fault detection in memories in comparison to conventional MBIST Architecture. The proposed MBIST Algorithm is optimized by using only 14 states for 7 March algorithms, hence improvising the scalability of the MBIST without area overhead. The proposed architecture has an interface check MISR which features isolated detection of fault in memory interface and memory, hence improving resolution and accuracy. Rapid Fault check is enabled by Memory pre-check using MISR. Benchmarking for this project in terms on the accuracy, feature enhancement, scalability and the ability to detect early faults in less time are done via Random constrained verification of the developed RTL Model.

Cite this Research Publication : Sasikumar Midhun, Sreehari K.N, Kumar Arjun S, Bhakthavatchalu, Ramesh," Scalable and Rapid Fault Detection of Memories Using MBIST and Signature Analysis",

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