Publication Type : Conference Paper
Publisher : Proceedings of the Custom Integrated Circuits Conference
Source : Proceedings of the Custom Integrated Circuits Conference, Institute of Electrical and Electronics Engineers Inc., San Jose, CA (2013)
ISBN : 9781467361460
Keywords : Analog to digital conversion, CMOS ADC, CMOS integrated circuits, CMOS technology, Four-channel, Integrated circuits, Pipelined ADCs, Time-interleaved, Timing calibration
Campus : Amritapuri
School : School of Engineering
Department : Electronics and Communication
Verified : Yes
Year : 2013
Abstract : A four-channel time-interleaved pipelined ADC employs a new timing calibration technique to suppress mismatch-induced spurs and achieve a Nyquist-rate SNDR of 44.4 dB. Designed in 65-nm CMOS technology, the ADC draws 120 mW, providing an FOM of 219 fJ per conversion step. © 2013 IEEE.
Cite this Research Publication : Ha Wei, Zhang, Pb, Sahoo, BcDatta, and Razavi, Ba, “An 8-Bit 4-GS/s 120-mW CMOS ADC”, in Proceedings of the Custom Integrated Circuits Conference, San Jose, CA, 2013.