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Block Level SoC Verification Using Systemverilog

Publication Type : Conference Paper

Publisher : Elsevier

Source : Proceedings of the 3rd International Conference on Electronics and Communication and Aerospace Technology, ICECA 2019

Url : https://www.scopus.com/record/display.uri?eid=2-s2.0-85072842737&origin=resultslist&sort=plf-f

Campus : Amritapuri

School : School of Engineering

Department : Electronics and Communication

Year : 2019

Abstract : Introducing a new strategy for verification of System On Chip (SoC) using system Verilog. System Verilog provides a great platform for verification. The OOPs concept in System Verilog make it more reliable. There are many existing SoC verification methods are available. But most of them are not that much efficient. So here we are planning to introduce a new verification strategy that takes many of the positive characteristics of the existing strategies and mixes them together to have an efficient and perfect strategy by using the advantages of System Verilog

Cite this Research Publication : Yadu, Krishnan K, Bhakthavatchalu, Ramesh "Block Level SoC Verification Using Systemverilog",Proceedings of the 3rd International Conference on Electronics and Communication and Aerospace Technology, ICECA 2019

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