Publication Type : Journal Article
Publisher : Institute of Electrical and Electronics Engineers (IEEE)
Source : IEEE Access
Url : https://doi.org/10.1109/access.2026.3680060
Campus : Chennai
School : School of Engineering
Year : 2026
Abstract : Accurate and robust grid synchronization is a critical requirement for inverter-dominated power systems to operate under non-stationary and distorted grid conditions. SRF-PLL is still widely adopted due to its structural simplicity; however, its dynamic performance is fundamentally bounded by the fixed-parameter proportional-integral (PI) loop filter, which enforces a trade-off between transient response and disturbance rejection. Motivated by these limitations, this paper proposes a hybrid physics-learning SRF-PLL framework wherein a long short-term memory neural network replaces the conventional PI loop filter while preserving the canonical PLL signal flow and structure. Unlike opaque system learning-based synchronizers, the proposed approach embeds the LSTM exclusively within the loop filter to achieve data-driven adaptive control synthesis via learning of the temporal evolution of synchronous reference-frame voltage errors. To further enhance robustness against modeling uncertainties, measurement noise, and unseen grid disturbances, an external residual phase-error-based adaptive correction mechanism is integrated to reinforce bounded closed-loop behavior in real time without affecting the parameters of the previously trained network. A disturbance-informed training strategy is developed using a rich set of nonlinear grid conditions pertaining to voltage sag/swell, phase jumps, frequency steps with ROCOF, voltage unbalance, harmonic distortion, and measurement noise. Comprehensive simulation studies demonstrate that the proposed LSTM-based SRF-PLL achieves faster settling, lower overshoot, and significantly improved frequency and phase tracking accuracy compared to PLL schemes based on GA, PBA, ANFIS, and GRU. Practical stability is examined through small-signal analysis, bounded-input bounded-output arguments, Lyapunov-based assessment, and extensive time-domain validation. Hardware-in-the-loop experiments conducted using the dSPACE DS1104 platform further corr...
Cite this Research Publication : P. Riyas, S. A. Lakshmanan, Data-Driven Loop Filter Design Using Long Short-Term Memory Networks for Enhanced Grid Synchronization in SRF-PLL System, IEEE Access, Institute of Electrical and Electronics Engineers (IEEE), 2026, https://doi.org/10.1109/access.2026.3680060