Publication Type : Conference Proceedings
Publisher : International Conference on Recent Innovations in Electrical, Electronics, Computer and Mechanical Engineering,
Source : International Conference on Recent Innovations in Electrical, Electronics, Computer and Mechanical Engineering, (ICRIEECME-Chennai). 2015.
Url : http://www.iraj.in/journal/journal_file/journal_pdf/12-178-1439024165122-126.pdf
Keywords : Alu; Double Gate Finfet (Dgfinfet); Delay; Half Adder; Half Subtractor; High Performance; Low Power
Campus : Bengaluru
School : School of Engineering
Department : Electrical and Electronics
Year : 2015
Abstract : we are moving towards the era of minimization of transistor size, short channel effects (SCEs) are becoming
major concern. Double gate FinFETs are emerging transistors, which gives better SCEs performance compared to
conventional Mosfet transistors .Adders and sub-tractors are very basic components in computation. Most of the operations
such as multiplication, division, ripple carry addition etc. require Adder and sub-tractor as a basic building block. The
efficiency of any system depends on the performance of internal components. If internal components satisfy the criteria of
area, power and delay, the system will always be a efficient system. The adders and sub-tractors are mainly used in
(arithmetic and logical units) ALUs. In this paper, area and (power delay product) PDP efficient common Half Adder-Half
sub-tractor cell design is presented at 32nm technology.
Cite this Research Publication : S. Yadav and Dantre, R., “Design and Analysis of FinFET Based High Performance 1 bit Half Adder-half Subtractor Cell”, International Conference on Recent Innovations in Electrical, Electronics, Computer and Mechanical Engineering, (ICRIEECME-Chennai). 2015.
