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Design of a High-Speed Binary Counter Using a Stacking Circuit

Publication Type : Journal Article

Source : Lecture Notes in Networks and Systems, Vol. 311, pp. 135-143,2022

Url : https://link.springer.com/chapter/10.1007/978-981-16-5529-6_11

Campus : Coimbatore

School : School of Engineering

Department : Electronics and Communication

Year : 2022

Abstract : A novel design of a binary counter is introduced in this paper. A 7:3 binary counter is designed using 5-bit and 2-bit stacking circuits, which is further merged and then converted into binary counts that bestow a binary stacking counter. This new design of binary stacking counter circuit does not have XOR gates or multiplexers in its critical path, which would turn out this circuit into a faster and efficient one. This innovative circuit is faster and has a better power efficiency which outperforms the conventional binary counter circuits. Hence, they find applications in deep learning and big data analysis

Cite this Research Publication : Devika C, J P Anita, “Design of a High-Speed Binary Counter Using a Stacking Circuit”, in Lecture Notes in Networks and Systems, Vol. 311, pp. 135-143,2022.

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