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Minimization of silicon area in high speed arithmetic circuits

Publication Type : Conference Proceedings

Publisher : Proceedings on National conference on Modeling, Analysis Simulation of Computers and Telecommunication systems(MASCOT)

Source : Proceedings on National conference on Modeling, Analysis & Simulation of Computers and Telecommunication systems(MASCOT), vol. Vol.1. pp. Pages 150-154, 2007.

Campus : Bengaluru

School : School of Engineering

Department : Electronics and Communication

Verified : No

Year : 2007

Abstract :

Cite this Research Publication : C Paramasivam, T. Kalavathidevi, M Rameshwaran (2007) “Minimization of silicon area in high speed arithmetic circuits”, Proceedings on National conference on Modeling, Analysis & Simulation of Computers and Telecommunication systems(MASCOT), Vol.1, Pages 150-154.

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