Programs
- Certificate Course on “Traditional Sculpture and Wood Carving” - Certificate
- Certificate Training Course in Diagnostic Flow Cytometry - Certificate
Publication Type : Conference Paper
Publisher : Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, Institute of Electrical and Electronics Engineers Inc.
Source : Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, Institute of Electrical and Electronics Engineers Inc., p.65-68 (2016)
ISBN : 9781467395458
Keywords : Block Matching, Burrows Wheeler transform, Compression ratio (machinery), Compression scheme, Data compression, Encoding (symbols), Memory requirements, Run length, Run-length encoding, Shannon, Test Data Compression, Timing circuits, VLSI circuits
Campus : Coimbatore
School : School of Engineering
Department : Electronics and Communication
Verified : No
Year : 2016
Abstract : A hybrid test data compression method is presented which is targeted at minimizing the volume of test data, which reduces memory requirements for test data and also time required to test the entire data. The compression scheme is so called hybrid as it combines a transform along with the encoding scheme. In the proposed approach, encoding schemes such as Frequency Directed Run length encoding and Shannon Fano encoding schemes are applied on the transformed data. The proposed scheme is applied on ISCAS'85, ISCAS'89 and ITC'99 benchmark circuits and compared in terms of their compression ratio. © 2016 IEEE.
Cite this Research Publication : A. Asokan and Dr. Anita J. P., “Multistage test data compression technique for VLSI circuits”, in Proceedings of 2016 International Conference on Advanced Communication Control and Computing Technologies, ICACCCT 2016, 2016, pp. 65-68.