Publications

Abstract : The proposed work has a test pattern generator for built-in self-test (BIST) based applications along with test data compression. Test patterns are produced with desired levels of toggling and improved fault coverage is obtained when compared with BIST-based pseudorandom pattern generators (PRPG). The pattern generator comprises of a pseudorandom pattern generation unit, a toggle generation and control unit, a hold register unit. Preselected toggling (PRESTO) generator allows user defined levels of toggling. The pattern generator is a linear finite state machine which drives a phase shifter, which reduces correlation of patterns. This paper proposes a test compression method which elevates the compression efficiency that has not been obtained by conventional compression techniques. It does not need any core logic modifications like test point insertion and thus the compression technique is nonintrusive. This hybrid technique of BIST along with test compression achieves fault coverage above 90%. Experimental results are obtained for ISCAS 85, ISCAS 89 and ITC 99 standard benchmark circuits. The PRESTO generator can effectively function as a decompressor also and hence area is reduced.